Metal Oxide Semiconductors (MOS) find use in integrated circuit devices, such as logic circuitry and memory devices. Exemplary memory include static random access memory (SRAM), dynamic random access memory (DRAM), and floating gate programmable read-only memories (i.e., PROMs, EPROMs, and EEPROMs). Such circuitry inevitably includes conductive lines connecting one or more devices together. One type of conductive line is a field effect transistor gate construction forming a portion of one or more field effect transistors. A gate is received proximate a channel region typically formed in lightly doped semiconductive material. Upon application of a suitable threshold voltage to the gate, a field is created in the channel region enabling current to flow through the channel region from a source region to a drain region. Alternately by way of example only, field effect transistor gate lines have also been utilized to establish fields therebeneath for creating isolation between circuitry components within a semiconductive substrate.
A field effect transistor gate line construction includes at least one conductive gate region and at least one gate dielectric region. The gate dielectric region is received intermediate the channel region and the conductive gate region. The common and predominantly used gate dielectric material has been SiO.sub.2. Yet, continued increase in circuit density and reduction in size of the field effect transistor gate constructions have reached the point where the thickness of silicon dioxide gate dielectric layers has become so small that leakage currents, reliability and defects have become problematic. Further, it is very difficult to grow very thin adequate silicon dioxide layers, such as less than 35 Angstroms, which may be desirable for advanced process flows, for example where gate width falls to 0.12 micron or less for logic processes.
One proposed prior art alternative to these challenges would be to use a material having a higher dielectric constant than SiO.sub.2. One example material is tantalum pentoxide (Ta.sub.2 O.sub.5). Such material has a higher dielectric constant than silicon dioxide and silicon nitride. However, Ta.sub.2 O.sub.5 apparently is problematic to use by itself in conventional constructions where the channel region and overlying conductive region of the gate comprise silicon or silicon compounds. For example, Ta.sub.2 O.sub.5 does not deposit with good stoichiometry. It typically deposits as Ta.sub.x O.sub.y which is then reoxidized to predominantly produce Ta.sub.2 O.sub.5. Such processing undesirably has an adverse effect on the interface of the Ta.sub.2 O.sub.5 with overlying and underlying materials. Further, it is apparently highly desirable to separate the tantalum of the Ta.sub.2 O.sub.5 from contacting the typical overlying conductively doped polysilicon of the conductive gate region to prevent undesired reactions from occurring between the polysilicon and tantalum in Ta.sub.2 O.sub.5. Accordingly where Ta.sub.2 O.sub.5 has been suggested for use as a gate dielectric material, the proposed use is a gate dielectric region comprising a stack of SiO.sub.2 /Ta.sub.2 O.sub.5 /SiO.sub.2 layers. Such a stack, however, apparently produces less than optimum effective dielectric thickness, particularly because SiO.sub.2 has a lower dielectric constant than Ta.sub.2 O.sub.5.